Computer Architectures

We are building a complex, hierarchical computing infrastructure revolving around the presence of FPGAs as basic computational blocks. Research is focused on both the interconnections between and among the components of the system.

Selected topics

Intra-accelerator, reconfiguration-aware FPGA mapping

At the lowest hierarchical level we have the Basic Block (BB). A BB is an FPGA-based hardware accelerator. A technique that automatizes the mapping of a computational blocks/agents found in the polyhedral network is required for an effective hardware mapping of software tasks to occur.

Intra-cluster, load-balancing aware multi node mapping

We target applications that expose large amount of parallelism, so we predict that we will require thousands of Nodes in our supercomputing system. Whenever this happens, scalability of the communication infrastructure becomes a critical aspect; this is the subject of this research.

Intra-node, interconnect-aware multi FPGA mapping

At the second lowest level in the hierarchy, we have the Cluster Node (N). N is a platform where multiple BBs are connect with each other via PCI Express, and share part of the computation, ideally the most communication-heavy one. A technique to choose how to partition a PPN on multiple BBs is the focus of this specific research.

Node and inter-node communication modeling

This research focuses on how to effectively connect multiple BBs and how to model the BB, in order to define the specifications of a BB prototype.

...and many more!

Think you might be interested in an exaFPGA-related thesis? Just drop an email to Riccardo Cattaneo !
(and have a look at the people and contacts section!)