Languages and Compilers

We are building a compilation suite specifically aimed at representing source code in a format which is useful for both making explicit opportunities for data-level parallelism as well as easing the mapping onto reconfigurable hardware.

Selected topics

Polyhedral Analysis (PA)

This is a fairly known (and old) technique in the languages and compilers field. It allows to explicitly represent the data-level parallelism present in a piece of code.

Polyhedral Process Networks (PPN)

This is a model of computations which is employed in combination with PA to represent an abstract computation where data-level parallelism is explicit.


A LLVM-based tool for PA. We plan on exploiting its internal representation of the PPN to extend exaFPGA.


The frontend for C-like languages. We plan to modify it to support additional features.


Hardware Description Languages (HDL) play a fundamental role in the race for efficiency. Our toolchain must support a methodology to translate the Intermediate Representation (IR) of LLVM (or at least a subset of it) to HDL in the most efficient possible way.

C-to-HDL: High Level Synthesis (HLS)

HLS is a powerful tool to "compile" an high-level, procedural language (like interesting subsets of C) to HDL directly, without any specific prior static code analysis. We focus on a subset of C codes for HLS.

...and many more!

Think you might be interested in an exaFPGA-related thesis? Just drop an email to Riccardo Cattaneo!
(and have a look at the people and contacts section!)